Method of removing spacers and fabricating mos transistor

ABSTRACT

A method of removing spacers after forming a MOS transistor on a wafer. The MOS transistor comprises a gate disposed on the substrate, spacers disposed on the sidewalls of the gate and a source and a drain region in the substrate beside the spacers. The spacers are removed by performing a wet etching process in the dark such that during the spacer removal process, the source and the drain region in a MOS transistor can be prevented from damages.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating a semiconductordevice. More particularly, the present invention relates to a method ofremoving spacers and fabricating metal-oxide-semiconductor (MOS)transistors.

2. Description of the Related Art

Metal-oxide-semiconductor (MOS) transistor is an important device in asemiconductor. FIG. 1A is schematic cross-sectional view of aconventional MOS transistor. As shown in FIG. 1A, a MOS transistor 20 isusually disposed on a substrate 100 (for example, a polysiliconsubstrate). The MOS transistor comprises a gate structure 122, a sourceregion 124 s, a drain region 124 d and spacers 126. The gate structure122 is disposed over the substrate 100. The gate structure 122 comprisesa gate dielectric layer 122 a and a gate layer 122 b sequentiallystacked over the substrate 100. The source region 124 s and the drainregion 124 d are disposed in the substrate 100 on the two sides of thegate structure 122, respectively. The spacers 126 are disposed on thesidewalls of the gate structure 122.

To improve the mobility of electrons and holes in the channel region(the region underneath the gate structure 122), the spacers 126 areoften removed using phosphoric acid in a wet etching operation after theprocess for fabricating the MOS transistor 120 is completed. Thereafter,a strain layer 130 is formed over the MOS transistor 120 and thesubstrate 100 to adjust the lattice structure of the substrate 100 (asshown in FIG. 1B).

However, electrons and holes would traverse the PN junction between thesource region 124 s and the substrate 100 as well as the drain region124 d and the substrate 100. When phosphoric acid is used to remove thespacers 126, the phosphoric acid and the electrons and holes at the PNjunction would trigger a photo-electrochemical reaction in the presenceof light. Ultimately, the source region 124 s and the drain region 124 dare damaged. This damaging effect is more serious for an NMOStransistor. FIG. 2 is a photo of an NMOS transistor taken by a scanningelectron microscope (SEM) showing the damages in the source and thedrain region when the spacers are removed using phosphoric acid in thepresence of light. As shown in FIG. 2, voids 128 (indicated by arrows)are formed in the source region 124 s and the drain region 124 d whenthe spacers 126 are removed using phosphoric acid in the present oflight.

SUMMARY OF THE INVENTION

Accordingly, one objective of the present invention is to provide amethod of removing spacers that can prevent the source and the drainregion of a metal-oxide-semiconductor (MOS) transistor from damages.

Another objective of the present invention is to provide a method offabricating a metal-oxide-semiconductor (MOS) transistor that canprevent the source and the drain region of the MOS transistor fromdamages with the method mentioned above.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides a method of removing spacers from the sidewalls of ametal-oxide-semiconductor (MOS) transistor. The MOS transistor comprisesa gate structure over a substrate, spacers on the sidewalls of the gatestructure and a source region and a drain region in the substrate besidethe spacers. The method of removing the spacers includes performing awet etching process in the dark.

In one embodiment of the present invention, the material of the spacersis silicon nitride, for example.

In one embodiment of the present invention, the wet etching process iscarried out using phosphoric acid, for example.

The present invention also provides a method of fabricating a MOStransistor. First, a gate structure is formed over a substrate. The gatestructure comprises a gate dielectric layer and a gate layersequentially stacked over the substrate. Thereafter, spacers are formedon the sidewalls of the gate structure. After that, a source region anda drain region are formed in the substrate beside the spacers. A wetetching process is carried out in the dark to remove the spacers on thesidewalls of the gate structure. Finally, a strain layer is formed overthe substrate to cover the gate structure and the substrate. The strainlayer mainly serves to adjust the lattice structure at the interfacewith the substrate.

In one embodiment of the present invention, the material of the spacersis silicon nitride, for example.

In one embodiment of the present invention, the wet etching process iscarried out using phosphoric acid, for example.

In one embodiment of the present invention, the material of the strainlayer is silicon oxide or silicon nitride, for example.

In one embodiment of the present invention, after forming the gatestructure but before forming the spacers, the method further includesforming a lightly doped drain (LDD) region in the substrate on each sideof the gate structure.

In the present invention, the process of removing the spacers from thesidewalls of the gate structure is carried out in total darkness. Hence,photochemical reaction at the source region and the drain region isprevented. In other words, damage to the source and the drain region canbe significantly minimized.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A is a schematic cross-sectional view of a conventional MOStransistor.

FIG. 1B is a schematic cross-sectional view of a conventional MOStransistor having a strain layer thereon.

FIG. 2 is a photo of an NMOS transistor taken by a scanning electronmicroscope (SEM) showing the damages in the source and the drain regionwhen the spacers are removed using phosphoric acid in the presence oflight.

FIGS. 3A through 3F are schematic cross-sectional views showing thesteps for fabricating a MOS transistor according to one embodiment ofthe present invention.

FIG. 4 is a photo of an NMOS transistor taken by a scanning electronmicroscope (SEM) showing the source and the drain region when thespacers are removed using phosphoric acid in darkness.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

FIGS. 3A through 3F are schematic cross-sectional views showing thesteps for fabricating a MOS transistor according to one embodiment ofthe present invention. As shown in FIG. 3A, a gate structure 220 isformed over a substrate 200. The gate structure 220 comprises a gatedielectric layer 222 and a gate layer 224 sequentially stacked over thesubstrate 200. The gate structure 220 is formed, for example, bydepositing a gate dielectric material and a gate material sequentiallyover the substrate to form a gate dielectric layer and a gate layer andthen performing a photolithographic and etching process. The gatedielectric layer 222 is a silicon oxide layer and the gate layer is apolysilicon or a silicide layer, for example.

As shown in FIG. 3B, lightly doped regions 262 are formed in thesubstrate 200 beside the gate structure 220. The lightly doped regions262 are formed, for example, by implanting dopants different from thosein the substrate 200 into the substrate 200 beside the gate structure220 in a thermal diffusion process or an ion implant process. In oneembodiment, the substrate is a p-type substrate and the dopants aren-type dopants (for example, phosphorus or arsenic).

As shown in FIG. 3C, spacers 240 are formed on the sidewalls of the gatestructure 220. The method of forming the spacers 240 includes, forexample, depositing spacer material over the gate structure 220 and thenperforming an anisotropic etching process. The anisotropic etchingprocess comprises a plasma etching operation. In addition, the materialof the spacers 240 is silicon nitride, for example.

As shown in FIG. 3D, a source region 260 s and a drain region 260 d areformed in the substrate 200 beside the spacers 240. The lightly dopedregions 262 underneath the spacers 240 now become lightly doped drain(LDD) regions capable of preventing short channel effect. The sourceregion 260 s and the drain region 260 d are formed, for example, bydiffusing dopants different from those in the substrate 200 into thesubstrate 200 beside the spacers 240 in a thermal diffusion process oran ion implant process. In one embodiment, the substrate is a p-typesilicon substrate and the dopants are n-type dopants (for example,phosphorus or arsenic).

To improve the mobility of electrons and holes inside the channel region(the region underneath the gate structure 220), the l lattice structurein the substrate 200 is slightly modified in the following.

As shown in FIG. 3E, a wet etching operation is carried out in anenvironment 300 without any light to remove the spacers 240 on thesidewalls of the gate structure 220. In one embodiment of the presentinvention, phosphoric acid is used as the etchant in the wet etchingoperation. Furthermore, the dark environment 300 in which the wetetching operation is carried out includes a dark room where no light isallowed to enter or other space or installation where light iscompletely blocked.

FIG. 4 is a photo of an NMOS transistor taken by a scanning electronmicroscope (SEM) showing the source and the drain region when thespacers are removed using phosphoric acid in darkness. When phosphoricacid is used to remove the spacers 240, the electrons and holestraversing the PN junction between the source region 260 s and thesubstrate 200 or the drain region 260 d and the substrate 200 would nottrigger a photochemical reaction due to the absence of light. Hence, thesource region 260 s and the drain region 260 d remain intact after thespacers are removed as shown in FIG. 4. Compared with the damage to thesource and the drain region shown in FIG. 2, the present invention ofremoving the spacers 240 in total darkness can really reduce the damageto the source region 260 s and the drain region 260 d.

As shown in FIG. 3F, a strain layer 280 is formed over the substrate 200to cover the gate structure 220 and the substrate 200. In the process offorming the strain layer 280, the lattice structure arrangement of thesubstrate 200 is modified. In one embodiment of the present invention,the strain layer 280 is a silicon oxide layer, a silicon nitride layeror other suitable materials, for example. Since a strain layer made ofsilicon oxide or silicon nitride has a larger lattice separation thanthat of the p-type silicon substrate 200, the p-type silicon latticearrangement in the substrate 200 will be adjusted according to thelattice structure of the strain layer 280. As the lattice separation ofthe p-type silicon substrate 200 increases to match that of the strainlayer 280, the mobility of the electrons and holes in the substrate 200also increases. Hence, the current will be enhanced to improve theperformance of the MOS transistor.

Obviously, the aforementioned method of removing the spacers is just oneof the applications and hence should not be used to limit the scope ofthe present invention. Although the aforementioned process offabricating the MOS transistor includes the step of forming a lightlydoped drain region, it can be applied to fabricate a MOS transistorwithout any lightly doped region as well.

In summary, the present invention has at least the followingadvantages: 1. The source region and the drain region are protected frompossible damage when the spacers are removed by carrying out a wetetching operation in the dark. Hence, overall yield of the MOStransistor is increased.

2. Using a strain layer to adjust the lattice separation of a substrate,the mobility of electrons within the substrate is increased. Hence,operating characteristics of the MOS transistor are improved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A method of removing spacers after forming ametal-oxide-semiconductor (MOS) transistor, wherein the MOS transistorcomprises a gate structure over a substrate, spacers on the sidewalls ofthe gate structure and a source region and a drain region in thesubstrate beside the gate structure; the method comprising the step ofperforming a wet etching process in a dark environment.
 2. The method ofclaim 1, wherein the material constituting the spacers comprises siliconnitride.
 3. The method of claim 2, wherein the etching agent forperforming the wet etching process comprises phosphoric acid.
 4. Amethod of fabricating a metal-oxide-semiconductor (MOS) transistor, themethod comprising: providing a substrate; forming a gate structure overthe substrate, wherein the gate structure comprises a gate dielectriclayer and a gate layer sequentially stacked over the substrate; formingspacers on the sidewalls of the gate structure; forming a source regionand a drain region in the substrate beside the gate structure;performing a wet etching process in a dark environment to remove thespacers on the sidewalls of the gate structure; and forming a strainlayer over the substrate to cover the gate structure and the substrate,wherein the strain layer is used for adjusting the lattice structure ofthe substrate.
 5. The method of claim 4, wherein the materialconstituting the spacers comprises silicon nitride.
 6. The method ofclaim 5, wherein the etching agent for performing the wet etchingprocess comprises phosphoric acid.
 7. The method of claim 4, wherein thematerial constituting the strain layer comprises silicon oxide orsilicon nitride.
 8. The method of claim 4, wherein after forming thegate structure but before forming the spacers, the method furthercomprises forming a lightly doped drain (LDD) region in the substratebeside the gate structure.